Difference: ForthSTM32WB (33 vs. 34)

Revision 342022-10-18 - PeterSchmid

Line: 1 to 1
 
META TOPICPARENT name="WebHome"
%DASHBOARD{ section="banner"
Line: 237 to 237
 Using USB_USER and the built-in bootloader (activate with jumper between CN7.5 and CN7.7) 
$ alias cubepgmcli='/opt/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin/STM32_Programmer_CLI'
Changed:
<
<		STM32Cube_FW_WB_V1.4.0/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwdelete STM32Cube_FW_WB_V1.4.0/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwupgrade stm32wb5x_FUS_fw.bin 0x080EC000 firstinstall=0 STM32Cube_FW_WB_V1.4.0/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwupgrade stm32wb5x_BLE_Stack_fw.bin 0x080CB000 firstinstall=1
>
>		STM32Cube_FW_WB_V1.4.1/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwdelete STM32Cube_FW_WB_V1.4.1/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwupgrade stm32wb5x_FUS_fw.bin 0x080EC000 firstinstall=0 STM32Cube_FW_WB_V1.4.1/Projects/STM32WB_Copro_Wireless_Binaries> cubepgmcli -c port=USB1 -fwupgrade stm32wb5x_BLE_Stack_full_fw.bin 0x080CE000 firstinstall=1
 
Changed:
<
<		Using ST-LINK (here to show the option bytes, SBRV : 0x32C00 means start address 4 * SBRV + 0x08000000 = 0x080CB000, 3D000 means there is no stack):
>
>		Using ST-LINK (here to show the option bytes, SBRV : 0x33800 means start address 4 * SBRV + 0x08000000 = 0x080CB000, 3D000 means there is no stack):
 
psi@homer:~/Dropbox/wbForth/CubeWB> cubepgmcli -c port=SWD -ob displ
      -------------------------------------------------------------------
Changed:
<
<		 STM32CubeProgrammer v2.3.0
>
>		 STM32CubeProgrammer v2.10.0
  -------------------------------------------------------------------
Changed:
<
<		ST-LINK SN : 066BFF313335415043141250 ST-LINK FW : V2J35M26 Voltage : 3,21V SWD freq : 4000 KHz Connect mode: Normal Reset mode : Software reset
>
>		Log output file: ob.log ST-LINK SN : 0030003E3137510539383538 ST-LINK FW : V3J10M3B5S1 Board : STLINK-V3SET Voltage : 3.27V SWD freq : 24000 KHz Connect mode: Under Reset Reset mode : Hardware reset
 Device ID : 0x495
Changed:
<
<		Device name : STM32WBxx
>
>		Revision ID : Rev Y Device name : STM32WB5x
 Flash size : 1 MBytes Device type : MCU
Changed:
<
<		Device CPU : Cortex-M0+/M4
>
>		Device CPU : Cortex-M4 BL Version : 0xd5 Debug in Low Power mode enabled
 

UPLOADING OPTION BYTES DATA ...

Bank : 0x00 Address : 0x58004020

Changed:
<
<		 Size : 104 Bytes
>
>		 Size : 96 Bytes
 
Changed:
<
<		[==================================================] 100%
>
>		 Bank : 0x01 Address : 0x58004080 Size : 8 Bytes
 

OPTION BYTES BANK: 0

Line: 279 to 286
  BOR Level:
Changed:
<
<		 BOR_LEV : 0x0 (BOR Level 0 reset level threshold is around 1.7 V)
>
>		 BOR_LEV : 0x4 (BOR Level 4 reset level threshold is around 2.8 V)
  User Configuration:

nBOOT0 : 0x1 (nBOOT0=1 Boot from main Flash) nBOOT1 : 0x1 (Boot from code area if BOOT0=0 otherwise system Flash)

Changed:
<
<		 nSWBOOT0 : 0x1 (BOOT0 taken from PH3/BOOT0 pin)
>
>		 nSWBOOT0 : 0x0 (BOOT0 taken from the option bit nBOOT0)
  SRAM2RST : 0x0 (SRAM2 erased when a system reset occurs) SRAM2PE : 0x1 (SRAM2 parity check disable) nRST_STOP : 0x1 (No reset generated when entering the Stop mode)
Line: 297 to 304
  IWDGSW : 0x1 (Software independent watchdog) IPCCDBA : 0x0 (0x0)
Changed:
<
<		 Security Configuration Option bytes:
>
>		 Security Configuration Option bytes - 1:
  ESE : 0x1 (Security enabled)
Deleted:
<
<		 SFSA : 0xCB (0xCB) FSD : 0x0 (System and Flash secure) DDS : 0x1 (CPU2 debug access disabled) C2OPT : 0x1 (SBRV will address Flash) NBRSD : 0x0 (SRAM2b is secure) SNBRSA : 0xF (0xF) BRSD : 0x0 (SRAM2a is secure) SBRSA : 0xA (0xA) SBRV : 0x32C00 (0x32C00)
  PCROP Protection:
Changed:
<
<		 PCROP1A_STRT : 0x1FF (0x8000FF8) PCROP1A_END : 0x0 (0x8000008) PCROP_RDP : 0x1 (PCROP zone is erased when RDP is decreased) PCROP1B_STRT : 0x1FF (0x8000FF8) PCROP1B_END : 0x0 (0x8000008)
>
>		 PCROP1A_STRT : 0x1FF (0x80FF800) PCROP1A_END : 0x0 (0x8000800) PCROP_RDP : 0x0 (PCROP zone is kept when RDP is decreased) PCROP1B_STRT : 0x1FF (0x80FF800) PCROP1B_END : 0x0 (0x8000800)
  Write Protection:
Changed:
<
<		 WRP1A_STRT : 0xFF (0x807F800)
>
>		 WRP1A_STRT : 0xFF (0x80FF000)
  WRP1A_END : 0x0 (0x8000000)
Changed:
<
<		 WRP1B_STRT : 0xFF (0x807F800)
>
>		 WRP1B_STRT : 0xFF (0x80FF000)
  WRP1B_END : 0x0 (0x8000000)
Added:
>
>		OPTION BYTES BANK: 1

Security Configuration Option bytes - 2:

SFSA : 0xC7 (0x80C7000) FSD : 0x0 (System and Flash secure) DDS : 0x1 (CPU2 debug access disabled) C2OPT : 0x1 (SBRV will address Flash) NBRSD : 0x0 (SRAM2b is secure) SNBRSA : 0xF (0x2003BC00) BRSD : 0x0 (SRAM2a is secure) SBRSA : 0xA (0x20032800) SBRV : 0x31C00 (0x20000000)

 
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